Fourth Semester B.Tech. Degree Examination, December 2009
(2003 Scheme)
03.406 – DIGITAL ELECTRONICS (TA)
Time : 3 Hours Max. Marks : 100
PART – A
Answer all questions. Each question carries 4 marks.
1. Minimise using K-map f?? ??(0,1,2,3,4,6,8,9,10).
2. Distinguish between decoder and demultiplexer.
3. Realise a full adder using half adders.
4. Write a entity declaration in VHDL for a 8:1 multiplexer.
5. Describe the advantages and disadvantages of a synchronous counter compared to
an asynchronous one.
6. What is race around condition ? Suggest three distinct steps to avoid it .
7. Convert (a) D flip-flop to T flip flop (b) JK flipflop to T flip flop.
8. Draw and explain the block diagram of a Moore sequential model.
9. Define and distinguish a critical race and non critical race in an asynchronous sequential
circuit.
10. Define and explain a static 0 and static 1 hazards. (10×4=40 Marks
PART – B
Answer any two questions from each module. Each question carries 10 marks.
(6×10=60 Marks)
MODULE – I
11. Using Quine Mc Cluskey method,minimise the function
J?? ??(1,3,4,6,9,11,12,14,17,19,20,22,25,27,28,30) ?? ??d(8,10,24,26) , finding all the
prime implicants and essential prime implicants. 10
12. a) Design an active high enable, active low output 2 to 4 line decoder using gates. 6
b) Implement f?? ?? (1,3,5,6) using single 4:1Mux. 4
13. a) Implement a 4 bit parallel adder using 74LS83 to perform both addition and
subtraction. Explain the logic behind the implementation with example. 6
b) Compare and contrast the static and dynamic RAM. 4
MODULE – II
14. Explain in detail, with circuit, the working of NOT, NAND and OR gates of CMOS. 10
15. Design a parity bit generator for the following : Inputs arrive in strings of 3 symbols
with two successive strings placed apart by single time units. The parity bit generator
is to be designed to insert parity bit in these spaces so that outcome is
continuous string of symbols without spaces. Use JK flipflops. 10
16. Design a synchronous counter to count the sequence
0 ?? 5 ?? 6 ?? 2 ?? 3 ??1 ?? 7 ?? 4 ?? 0 ?? 5 ?? 6 ?? ...... Use JK flip flop. 10
MODULE – III
17. Construct a state diagram for a Mealy sequential machine that will detect the
following input sequences : x=01101 or 01111. If input sequence x=01101 is met,
cause z1=1. If x=01111 is met, cause Z2=1. Each input sequence may overlap with
itself or the other sequence. 10
-3- 8080
18. Consider the state diagram table given below :
Present
state
Next state x,y/z
00 Z 01 Z 11 Z 10 Z
A B 0 C 0 B 1 A 0
B E 0 C 0 B 1 D 1
C A 0 B 0 C 1 D 1
D C 0 D 0 A 1 B 0
E C 0 C 0 C 1 E 0
Draw the state diagram for this Mealy machine and deduce the implication chart,
deteremining whether there are any redundant states are there. Obtain the simplified
Mealy state diagram . 10
19. a) Explain why a maxterm circuit cannot generate a static 1 hazard. 4
b) Draw and explain a typical circuit generating a static-0 hazard with the help of
timing diagram. Why are two levels of logic necessary to generate static
hazards? 6
———————
(2003 Scheme)
03.406 – DIGITAL ELECTRONICS (TA)
Time : 3 Hours Max. Marks : 100
PART – A
Answer all questions. Each question carries 4 marks.
1. Minimise using K-map f?? ??(0,1,2,3,4,6,8,9,10).
2. Distinguish between decoder and demultiplexer.
3. Realise a full adder using half adders.
4. Write a entity declaration in VHDL for a 8:1 multiplexer.
5. Describe the advantages and disadvantages of a synchronous counter compared to
an asynchronous one.
6. What is race around condition ? Suggest three distinct steps to avoid it .
7. Convert (a) D flip-flop to T flip flop (b) JK flipflop to T flip flop.
8. Draw and explain the block diagram of a Moore sequential model.
9. Define and distinguish a critical race and non critical race in an asynchronous sequential
circuit.
10. Define and explain a static 0 and static 1 hazards. (10×4=40 Marks
PART – B
Answer any two questions from each module. Each question carries 10 marks.
(6×10=60 Marks)
MODULE – I
11. Using Quine Mc Cluskey method,minimise the function
J?? ??(1,3,4,6,9,11,12,14,17,19,20,22,25,27,28,30) ?? ??d(8,10,24,26) , finding all the
prime implicants and essential prime implicants. 10
12. a) Design an active high enable, active low output 2 to 4 line decoder using gates. 6
b) Implement f?? ?? (1,3,5,6) using single 4:1Mux. 4
13. a) Implement a 4 bit parallel adder using 74LS83 to perform both addition and
subtraction. Explain the logic behind the implementation with example. 6
b) Compare and contrast the static and dynamic RAM. 4
MODULE – II
14. Explain in detail, with circuit, the working of NOT, NAND and OR gates of CMOS. 10
15. Design a parity bit generator for the following : Inputs arrive in strings of 3 symbols
with two successive strings placed apart by single time units. The parity bit generator
is to be designed to insert parity bit in these spaces so that outcome is
continuous string of symbols without spaces. Use JK flipflops. 10
16. Design a synchronous counter to count the sequence
0 ?? 5 ?? 6 ?? 2 ?? 3 ??1 ?? 7 ?? 4 ?? 0 ?? 5 ?? 6 ?? ...... Use JK flip flop. 10
MODULE – III
17. Construct a state diagram for a Mealy sequential machine that will detect the
following input sequences : x=01101 or 01111. If input sequence x=01101 is met,
cause z1=1. If x=01111 is met, cause Z2=1. Each input sequence may overlap with
itself or the other sequence. 10
-3- 8080
18. Consider the state diagram table given below :
Present
state
Next state x,y/z
00 Z 01 Z 11 Z 10 Z
A B 0 C 0 B 1 A 0
B E 0 C 0 B 1 D 1
C A 0 B 0 C 1 D 1
D C 0 D 0 A 1 B 0
E C 0 C 0 C 1 E 0
Draw the state diagram for this Mealy machine and deduce the implication chart,
deteremining whether there are any redundant states are there. Obtain the simplified
Mealy state diagram . 10
19. a) Explain why a maxterm circuit cannot generate a static 1 hazard. 4
b) Draw and explain a typical circuit generating a static-0 hazard with the help of
timing diagram. Why are two levels of logic necessary to generate static
hazards? 6
———————
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