Fourth Semester B.Tech. Degree Examination, December 2009
(2003 Scheme)
03.403 : DIGITAL ELECTRONICS AND LOGIC DESIGN (E)
Time : 3 Hours Max. Marks : 100
Instruction: Part A is compulsory. Answer one full question from each
Module in Part B.
PART – A
Answer all questions :
1. In what ways digital circuits are superior to analog circuits.
2. Give the truth table and circuit of a half subtractor.
3. Realise the function f ?? AB ?? CD ?? B using NOR gates.
4. Explain race-around problem. Mention the ways to eliminate it.
5. Draw the internal circuit details of a TTL NAND gate.
6. Perform the following BCD addition
i) 1001 + 0100
ii) 01100111 + 01010011
7. Draw the internal circuitary of 555 IC timer.
8. Write a short note on Schottky transistors.
9. What are the different methods of representing negative numbers ?
10. State and explain sampling theorem. (4×10=40 Marks)
PART – B
Answer one full question from each Module.
Module – I
11. a) Explain weighted codes, unweighted codes and alphanumeric codes.
b) Convert the following :
i) 227.5810 to XS-3 code
ii) (1101.011)2 to decimal
iii) (236)10 to hexadecimal
iv) DADA16 to Octal
12. a) State and prove De-Morgans theorem of Boolean algebra.
b) Perform the following binary subtractions using 2s complement
i) 110011 – 00010000
ii) 01100 – 00011
iii) 0011.1001 – 0001.1110
Module – II
13. a) Give the internal circuitry of CMOS NAND gate and explain its operation.
b) Design a parity checker/generator and explain the working of the same.
14. a) Find the minimal POS expression for F (W, X, Y, Z) = ?? (1, 4, 5, 6, 11, 12, 13, 14, 15)
b) Draw the logic diagram of a full subtractor using the NAND gates.
Module – III
15. a) Draw the circuit of a 4 bit binary up/down counter and explain its operation.
b) Design and explain BCD to 7 segment decoder.
16. a) Explain the operation of a shift register. Show how it can be used for serial to
parallel conversion of a data sequence.
b) Draw the circuit of a D flip flop using NAND gates only and verify its truth table.
(20×3=60 Marks)
–––––––––––––––––
(2003 Scheme)
03.403 : DIGITAL ELECTRONICS AND LOGIC DESIGN (E)
Time : 3 Hours Max. Marks : 100
Instruction: Part A is compulsory. Answer one full question from each
Module in Part B.
PART – A
Answer all questions :
1. In what ways digital circuits are superior to analog circuits.
2. Give the truth table and circuit of a half subtractor.
3. Realise the function f ?? AB ?? CD ?? B using NOR gates.
4. Explain race-around problem. Mention the ways to eliminate it.
5. Draw the internal circuit details of a TTL NAND gate.
6. Perform the following BCD addition
i) 1001 + 0100
ii) 01100111 + 01010011
7. Draw the internal circuitary of 555 IC timer.
8. Write a short note on Schottky transistors.
9. What are the different methods of representing negative numbers ?
10. State and explain sampling theorem. (4×10=40 Marks)
PART – B
Answer one full question from each Module.
Module – I
11. a) Explain weighted codes, unweighted codes and alphanumeric codes.
b) Convert the following :
i) 227.5810 to XS-3 code
ii) (1101.011)2 to decimal
iii) (236)10 to hexadecimal
iv) DADA16 to Octal
12. a) State and prove De-Morgans theorem of Boolean algebra.
b) Perform the following binary subtractions using 2s complement
i) 110011 – 00010000
ii) 01100 – 00011
iii) 0011.1001 – 0001.1110
Module – II
13. a) Give the internal circuitry of CMOS NAND gate and explain its operation.
b) Design a parity checker/generator and explain the working of the same.
14. a) Find the minimal POS expression for F (W, X, Y, Z) = ?? (1, 4, 5, 6, 11, 12, 13, 14, 15)
b) Draw the logic diagram of a full subtractor using the NAND gates.
Module – III
15. a) Draw the circuit of a 4 bit binary up/down counter and explain its operation.
b) Design and explain BCD to 7 segment decoder.
16. a) Explain the operation of a shift register. Show how it can be used for serial to
parallel conversion of a data sequence.
b) Draw the circuit of a D flip flop using NAND gates only and verify its truth table.
(20×3=60 Marks)
–––––––––––––––––
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